1. Field of the Invention
The present invention relates to dynamic logic and register functions, and more particularly to a non-inverting domino register that addresses the problem of registering the outputs of complex logic circuits where speed and size are important factors.
2. Description of the Related Art
Integrated circuits use a remarkable number of registers, particularly those having a synchronous pipeline architecture. Register logic is employed to hold the outputs of devices and circuits for a period of time so that these outputs can be received by other devices and circuits. In a clocked system, such as a pipeline microprocessor, registers are used to latch and hold the outputs of a given pipeline stage for a period of one clock cycle so that input circuits in a subsequent stage can receive the outputs during that period while the given pipeline stage is concurrently generating new outputs.
In the past, it has been common practice to precede and follow complex logical evaluation circuits, such as multiple input multiplexers (muxes), multi-bit encoders, etc., with registers to hold the inputs to and the outputs from the evaluation circuits. Generally, these registers have associated setup and hold time requirements, both of which constrain the evaluation circuits in the preceding stage. In addition, registers have corresponding data-to-output time characteristics, which constrain the evaluation circuits in subsequent stages. The “speed” of a register is typically judged in terms of its data-to-output time, that is, the sum of its setup time and clock-to-output time.
Preceding and following a logical evaluation circuit with traditional register circuits introduces delays into a pipeline system whose cumulative effect results in significantly slower operating speeds. More specifically, one notable source of these delays is the data-to-output time requirements that must be satisfied by logical evaluation circuits in order to ensure stable registered outputs. It is desired to reduce these delays to provide additional time in each stage and to thereby increase overall speed of the pipeline system.
FIG. 1A is a schematic diagram of a traditional inverting domino register 100. The inverting domino register 100 attempts to address one aspect of the above-described problems, which enables logic designers combine logic evaluation functions with their corresponding registers. The inverting domino register 100 includes a logic evaluation input stage, or domino stage, which consists of stacked P-channel and N-channel devices P1, N1 and N2. P1 and N2 are a complementary pair of evaluation devices and N1 represents evaluation logic. The source of P1 is coupled to a voltage source VDD and its drain is coupled to node 105 providing a signal TOP. The drain of N1 is coupled to node 105 and its source is coupled to the drain of N2. The source of N2 is coupled to ground. An input clock signal CLK is provided via node 101 to the gates of P1 and N2. An input data signal DATA is provided via node 103 to the gate of N1.
The domino stage is followed by a storage stage, a weak keeper circuit 111, and, for noise reduction, at least one inverter/buffer 109. The storage stage includes devices P2, N3 and N4. Node 101 is coupled to the gate of N3 and node 105 is coupled to the gates of P2 and N4. The source of P2 is coupled VDD and its drain is coupled to node 107 providing an intermediate output signal QBI. Node 107 is coupled to the input of the inverter 109, to the drain of N3 and to the weak keeper circuit 111. The source of N3 is coupled to the drain of N4, which has its source coupled to ground. The keeper circuit 111 includes a first inverter 111A having its input coupled to node 107 for receiving the QBI signal and its output coupled to the input of a second inverter 111B, which has its output coupled to node 107. The inverter 109 has an output coupled to node 113 providing an inverting output signal QB. As described further below, an additional inverter/buffer 115, shown using phantom lines, may be added having its input coupled to node 113 and its output coupled to node 117 providing a non-inverted output signal Q.
FIG. 1B is a timing diagram illustrating operation of the inverting domino register 100, in which the CLK, DATA, TOP, QBI, QB and Q signals are plotted versus time. At a time TO when the CLK signal is initially low, N2 is turned off and P1 is turned on, so that the domino stage pre-charges the TOP signal high. The TOP signal is pre-charged high in preparation for evaluation of the DATA signal upon the rising edge of CLK. The DATA signal is initially high. Since TOP is high, device P2 is off and since CLK is low, device N3 is off. This isolates signal QBI from the input stage so that it remains at its former state and is held there by the keeper circuit 111. As shown, the QBI signal is initially low at time T0 and the QB signal is initially driven high by the inverter/buffer 109. The inverter/buffer 109 protects the output of the keeper circuit 111 from the adverse affects of noise and yields output QB, which is an inverted state of the logic function evaluation of the DATA signal.
At subsequent time T1, the CLK signal is asserted high which turns N2 on and P1 off. Since the DATA signal is high at time T1, N1 is also on so that the TOP signal is discharged low after a short delay through N1 and N2. Negligible delays are ignored in the timing diagrams. The QBI signal is also asserted high at about time T1, and the QB signal is asserted low at time T2 after the delay through the inverter/buffer 109. The CLK signal subsequently goes low at time T4 and the TOP signal is pre-charged high once again by P1. Signal QBI is once again isolated from the input stage by devices P2 and N3, so the state of the QBI signal remains high via operation of the keeper circuit 111, and the QB remains low. At subsequent time T5, the CLK signal is once again asserted high while the DATA signal is low, so that N1 and P1 are both off. The TOP signal remains high so that both N3 and N4 are turned on discharging the QBI signal low at about time T5. The QB goes high at time T6 after the delay through the inverter/buffer 109. The respective states of the TOP, QBI and QB signals remain unchanged throughout the remainder of the clock cycle including when the CLK signal next goes low at time T8. The only constraint placed on the DATA signal is that it remains unchanged while the signal CLK is high. CLK is usually a pulse having a short high time.
It is noted that the inverting domino register 100 is implemented as a simple D flip-flop in which N1 is used as the sole device in the evaluation circuit for evaluating the DATA signal (i.e., the D input). As appreciated by those of ordinary skill in the art, however, more complex logic evaluation functions can be substituted in place of device N1. The domino register is considered “inverting” since the QB output signal is asserted to the opposite state of the DATA input signal evaluated upon each rising edge of CLK. If the inverter/buffer 115 is included, as further described below, then the state of the Q signal follows the QBI signal after the delays through both of the inverters 109 and 115. As shown, the Q signal goes high at time T3 after the delay through the inverter/buffer 115 in response to QB going low at time T2, and the Q signal goes low again at time T7 in response to QB going high at time T6.
The inverting domino register 100 exhibits a minimized setup time and an acceptable data-to-out time under conditions in which an inverted state of the logic evaluant is acceptable. In cases in which a non-inverted registered output is required, however, designers have been forced to deal with disadvantageous consequences. To produce the non-inverted output Q, designers typically had to add the inverter 115 to invert QB to provide the non-inverted output Q. This workaround, however, inserted additional delay to the register. As shown, for example, the delay through the inverter/buffer 115 from times T2 to T3 and T6 to T7 is added to the delay through the inverter/buffer 109 from times T1 to T2 and T5 to T6, respectively. The delays are increased using larger buffer devices with increased capacitance. It is noted that the delay through the inverter 109 may be reduced somewhat by reducing its size if the inverter/buffer 115 is provided to drive the output. Nonetheless, the total delay remains significant for the non-inverting case. For devices implemented using a 0.18 micron process, for example, the additional delay is approximately 30 picoseconds (ps).
In time-critical paths, an alternative workaround is to take the intermediate output signal QBI as the registered output. This second alternative, however, exposes the weak keeper circuit 111 to noise conditions under which the stability of the QBI signal is put at risk. Hence, in order to produce a non-inverted output, the state of the art for domino-type registers required that designers either accept additional delay or risk stability of the output.